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1 ? fn6930.0 ISL62873 pwm dc/dc controller with vid inputs for portable gpu core-voltage regulator the ISL62873 is a single-p hase synchronous-buck pwm voltage regulator featuring intersil?s robust ripple regulator (r 3 ) technology?. the wide 3.3v to 25v input voltage range is ideal for systems that run on battery or ac-adapter power sources. the ISL62873 is a low-co st solution for applications requiring dynamically selected slew-rate controlled output voltages. the soft-start and dynamic setpoint slew-rates are capacitor programmed. voltage identification logic-inputs select two resistor-programmed setpoint reference voltages that directly set the output voltage of the converter between 0.5v to 1.5v, and up to 3.3v using a feedback voltage divider. optionally, an external referenc e such as the dac output from a microcontroller, can be used by either ic to program the setpoint reference voltage, and still maintain the controlled slew-rate features. robust inte grated mosfet drivers and schottky bootstrap diode reduce the implementation area and lower component cost. intersil?s r 3 technology? combines the best features of both fixed-frequency and hyster etic pwm control. the pwm frequency is 300khz during static operation, becoming variable during changes in load, setpoint voltage, and input voltage when changing between battery and ac-adapter power. the modulators ability to change the pwm switching frequency during these events in conjunction with external loop compensation produces su perior transient response. for maximum efficiency, the converter automatically enters diode-emulation mode (dem) during light-load conditions such as system standby. features ? input voltage range: 3.3v to 25v ? output voltage range: 0.5v to 3.3v ? output load up to 30a ? flexible output voltage programmability - 1-bit vid selects two independent setpoint voltages - simple resistor programming of setpoint voltages - accepts external setpoint reference such as dac ? 0.75% system accuracy: -10c to +100c ? one capacitor programs soft-start and setpoint slew-rate ? fixed 300khz pwm frequency in continuous conduction ? external compensation affords optimum control loop tuning ? automatic diode emulation mode for highest efficiency ? integrated high-current mosfet drivers and schottky boot-strap diode for optimal efficiency ? choice of overcurrent detection schemes - lossless inductor dcr current sensing - precision resistive current sensing ? power-good monitor for soft -start and fault detection ? fault protection - undervoltage - overcurrent (dcr-sense or resistive-sense capability) - over-temperat ure protection - fault identification by pg ood pull-down resistance ? pb-free (rohs compliant) applications ? mobile pc graphical processing unit vcc rail ? mobile pc i/o controller hub (ich) vcc rail ? mobile pc memory controller hub (gmch) vcc rail ? built-in voltage margin for system-level test pinout ISL62873 (16 ld 2.6x1.8 tqfn) top view 12 11 10 9 16 15 14 13 5 6 7 8 1 2 3 4 gnd en vid0 sref boot ugate phase ocset pgnd lgate pvcc vcc set0 pgood fb vo ordering information part number (note) temp range (c) package (pb-free) pkg. dwg. # ISL62873hruz-t* -10 to +100 16 ld 2.6x1.8 tqfn tape and reel l16.2.6x1.8a *please refer to tb347 for detai ls on reel specifications. note: these intersil pb-free plas tic packaged products employ special pb-free material sets; molding compounds/die attach materials and nipdau plate - e4 te rmination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet june 30, 2009 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2009. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6930.0 june 30, 2009 ISL62873 block diagram pgnd pvcc uvp + ? por vid0 vid decoder set0 sref boot lgate driver ugate driver phase vo ocset + ? ocp v set fb pgood sw1 sw0 100pf sw4 vref figure 1. simplified functional block diagram of ISL62873 100k vcc int gnd i ocset 10f + ? + ? + ? c r h l in vcc pwm v w en pwm run run run fault ext 500mv g m v o g m v in v r v comp + ? ea fb protection shoot-through otp fault
3 fn6930.0 june 30, 2009 application schematics figure 2. ISL62873 application schematic with tw o output voltage setpoints and dcr current sense figure 3. ISL62873 application schematic with two output voltage setpoints and resistor current sense en gnd sref vid0 c boot l o co c c ocset r ocset q hs q ls c comp r comp r fb 3.3v to 25v 0.5v to 3.3v r o co b cin c cin b v in v out c soft r set1 r set2 c vcc c pvcc gpio gpio 8 7 6 5 13 14 15 16 vo fb pgood set0 vcc pvcc lgate pgnd 11 ugate boot 2 112 9 ocset phase 4 310 +5v r vcc r pgood vcc r ofs en gnd sref vid0 c boot l o co c c ocset r ocset q hs q ls c comp r comp r fb 3.3v to 25v 0.5v to 3.3v r o co b cin c cin b v in v out c soft r set1 r set2 c vcc c pvcc gpio 8 7 6 5 13 14 15 16 vo fb pgood set0 vcc pvcc lgate pgnd 11 ugate boot 2 112 9 ocset phase 4 310 +5v r vcc gpio r pgood vcc r ofs r sns ISL62873
4 fn6930.0 june 30, 2009 figure 4. ISL62873 application schematic with external reference input and dcr current sense application schematics (continued) en gnd sref vid0 c boot l o co c c ocset r ocset q hs q ls c comp r comp r fb 3.3v to 25v 0.5v to 3.3v r o co b cin c cin b v in v out c vcc c pvcc gpio 8 7 6 5 13 14 15 16 vo fb pgood set0 vcc pvcc lgate pgnd 11 ugate boot 2 112 9 ocset phase 4 310 +5v r vcc r ofs c soft ext_ref gpio r pgood vcc ISL62873
5 fn6930.0 june 30, 2009 absolute m aximum ratings vcc, pvcc, pgood to gnd . . . . . . . . . . . . . . . . . . -0.3v to +7.0v vcc, pvcc to pgnd . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7.0v gnd to pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v en, set0, vo, vid0, fb, ocset, sref. . . . . . . . . . . . -0.3v to gnd, vcc + 0.3v boot voltage (v boot-gnd ). . . . . . . . . . . . . . . . . . . . . -0.3v to 33v boot to phase voltage (v boot-phase ) . . . . . . -0.3v to 7v (dc) -0.3v to 9v (<10ns) phase voltage . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 28v gnd -8v (<20ns pulse width, 10j) ugate voltage . . . . . . . . . . . . . . . . v phase - 0.3v (dc) to v boot v phase - 5v (<20ns pulse width, 10j) to v boot lgate voltage . . . . . . . . . . . . . . . gnd - 0.3v (dc) to vcc + 0.3v gnd - 2.5v (<20ns pulse width, 5j) to vcc + 0.3v thermal information thermal resistance (typical, note 1) ja (c/w) 16 ld tqfn package . . . . . . . . . . . . . . . . . . . . . . 84 junction temperature range. . . . . . . . . . . . . . . . . .-55 c to +150 c operating temperature range . . . . . . . . . . . . . . . .-10 c to +100 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65 c to +150 c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions ambient temperature range. . . . . . . . . . . . . . . . . .-10c to +100c converter input voltage to gnd . . . . . . . . . . . . . . . . . . 3.3v to 25v vcc, pvcc to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5v 5% caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. electrical specifications these specifications apply for t a = -10c to +100c, unless otherwise stated. all typical specifications t a = +25c, vcc = 5v. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characteriza tion and are not production tested. parameter symbol test conditions min typ max unit vcc and pvcc vcc input bias current i vcc en = 5v, vcc = 5v, fb = 0.55v, sref < fb - 1.1 1.5 ma vcc shutdown current i vccoff en = gnd, vcc = 5v - 0.1 1.0 a pvcc shutdown current i pvccoff en = gnd, pvcc = 5v - 0.1 1.0 a vcc por threshold rising vcc por threshold voltage v vcc_thr 4.40 4.49 4.60 v falling vcc por threshold voltage v vcc_thf 4.10 4.22 4.35 v regulation reference voltage v ref(int) -0.50- v system accuracy vid0 = vid1 = gnd, pwm mode = ccm -0.75 - +0.75 % pwm switching frequency f sw pwm mode = ccm 270 300 330 khz vo vo input voltage range v vo 0-3.6v vo input impedance r vo en = 5v - 600 - k vo reference offset current i voss v enthr < en, sref = soft-start mode - 10 - a vo input leakage current i vooff en = gnd, vo = 3.6v - 0.1 - a error amplifier fb input bias current i fb en = 5v, fb = 0.50v -20 - +50 na sref sref operating voltage range v sref nominal sref setting with 1% resistors 0.5 - 1.5 v soft-start current i ss sref = soft-start mode 10 20 30 a voltage step current i vs sref = setpoint-stepping mode 60 100 140 a ISL62873
6 fn6930.0 june 30, 2009 external reference extref operating voltage range v ext set0 = vcc 0 - 1.5 v extref accuracy v ext_ofs set0 = vcc, vid0 = 0v to 1.5v -0.5 - +0.5 % power good pgood pull-down impedance r pg_ss pgood = 5ma sink 75 95 150 r pg_uv pgood = 5ma sink 75 95 150 r pg_ov pgood = 5ma sink 50 65 90 r pg_oc pgood = 5ma sink 25 35 50 pgood leakage current i pg pgood = 5v - 0.1 1.0 a pgood maximum sink current (note 2) i pg_max -5.0-ma gate driver ugate pull-up resistance (note 2) r ugpu 200ma source current - 1.0 1.5 ugate source current (note 2) i ugsrc ugate - phase = 2.5v - 2.0 - a ugate sink resistance (note 2) r ugpd 250ma sink current - 1.0 1.5 ugate sink current (note 2) i ugsnk ugate - phase = 2.5v - 2.0 - a lgate pull-up resistance (note 2) r lgpu 250ma source current - 1.0 1.5 lgate source current (note 2) i lgsrc lgate - gnd = 2.5v - 2.0 - a lgate sink resistance (note 2) r lgpd 250ma sink current - 0.5 0.9 lgate sink current (note 2) i lgsnk lgate - pgnd = 2.5v - 4.0 - a ugate to lgate deadtime t ugflgr ugate falling to lgate rising, no load - 21 - ns lgate to ugate deadtime t lgfugr lgate falling to ugate rising, no load - 21 - ns phase phase input impedance r phase -33-k bootstrap diode forward voltage v f pvcc = 5v, i f = 2ma - 0.58 - v reverse leakage i r v r = 25v - 0.2 - a control inputs en high threshold voltage v enthr 2.0 - - v en low threshold voltage v enthf --1.0v en input bias current i en en = 5v 1.5 2.0 2.5 a en leakage current i enoff en = gnd - 0.1 1.0 a vid<0,1> high threshold voltage v vidthr 0.6 - - v vid<0,1> low threshold voltage v vidthf --0.5v vid<0,1> input bias current i vid en = 5v, v vid = 1v - 0.5 - a vid<0,1> leakage current i vidoff -0-a protection ocp threshold voltage v ocpth v ocset - v o -1.15 - 1.15 mv ocp reference current i ocp en = 5.0v 9.3 10 10.5 a ocset input resistance r ocset en = 5.0v - 600 - k ocset leakage current i ocset en = gnd - 0 - a uvp threshold voltage v uvth v fb = %v sref 81 84 87 % electrical specifications these specifications apply for t a = -10c to +100c, unless otherwise stated. all typical specifications t a = +25c, vcc = 5v. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characteriza tion and are not production tested. (continued) parameter symbol test conditions min typ max unit ISL62873
7 fn6930.0 june 30, 2009 functional pin descriptions gnd (pin 1) ic ground for bias supply and signal reference. en (pin 2) enable input for the ic. pulling en above the v enthr rising threshold voltage initializes the soft-start sequence. vid0 (pin 3) logic input for setpoint voltage selector. use to select between the two setpoint reference voltages. external reference input when enabled by connecting the set0 pin to the vcc pin. sref (pin 4) soft-start and voltage slew-rate programming capacitor input. setpoint reference voltage programming resistor input. connects internally to the inverting input of the v set voltage setpoint amplifier. see figure 5 on page 9 for capacitor and resistor connections. set0 (pin 5) voltage set-point programming resistor input. see figure 5 on page 9 for resistor connection. pgood (pin 6) power-good open-drain indicator output. this pin changes to high impedance when the converter is able to supply regulated voltage. the pull-down resistance between the pgood pin and the gnd pin identifies which protective fault has shut down the regulator. see table 2 on page 12. fb (pin 7) voltage feedback sense input. connects internally to the inverting input of the control-loop error amplifier. the converter is in regulation when the voltage at the fb pin equals the voltage on the sref pin. the control loop compensation network connects between the fb pin and the converter output. see figure 9 on page 13. vo (pin 8) output voltage sense input for the r 3 modulator. the vo pin also serves as the reference input for the overcurrent detection circuit. see figure 6 on page 10. ocset (pin 9) input for the overcurrent detection circuit. the overcurrent setpoint programming resistor r ocset connects from this pin to the sense node. see figure 6 on page 10. phase (pin 10) return current path for th e ugate high-side mosfet driver. v in sense input for the r 3 modulator. inductor current polarity detector input. connect to junction of output inductor, high-side mosfet, and low-side mosfet. see ?application schematics? (figures 2 and 3) on page 3. ugate (pin 11) high-side mosfet gate driver output. connect to the gate terminal of the high-side mosfet of the converter. boot (pin 12) positive input supply for the ugate high-side mosfet gate driver. the boot pin is internally connected to the cathode of the schottky boot-strap diode. connect an mlcc between the boot pi n and the phase pin. vcc (pin 13) input for the ic bias voltage. connect +5v to the vcc pin and decouple with at least a 1f mlcc to the gnd pin. see ?application schematics? (figures 2 and 3) on page 3. pvcc (pin 14) input for the lgate and ugat e mosfet driver circuits. the pvcc pin is internally connected to the anode of the schottky boot-strap diode. connect +5v to the pvcc pin and decouple with a 10f mlcc to the pgnd pin. see ?application schematics? (figures 2 and 3) on page 3. lgate (pin 15) low-side mosfet gate driver output. connect to the gate terminal of the low-side mosfet of the converter. pgnd (pin 16) return current path for the lgate mosfet driver. connect to the source of the low-side mosfet. setpoint reference voltage programming voltage identification (vid) pins select user-programmed setpoint reference voltages that appear at the sref pin. the converter is in regulation when the fb pin voltage (v fb ) otp rising threshold temperature (note 2) t otrth -150- c otp hysteresis (note 2) t othys -25-c note: 2. limits established by characterization and are not production tested. electrical specifications these specifications apply for t a = -10c to +100c, unless otherwise stated. all typical specifications t a = +25c, vcc = 5v. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characteriza tion and are not production tested. (continued) parameter symbol test conditions min typ max unit ISL62873
8 fn6930.0 june 30, 2009 equals the sref pin voltage (v sref .) the ic measures v fb and v sref relative to the gnd pin, not the pgnd pin. the setpoint reference voltages use the naming convention v set(x) where (x) is the first, second, third, or fourth setpoint reference voltage where: -v set1 < v set2 < v set3 < v set4 -v out1 < v out2 < v out3 < v out4 the v set1 setpoint is fixed at 500mv because it corresponds to the closure of internal switch sw0 that configures the v set amplifier as a unity-gain voltage follower for the 500mv voltage reference v ref . a feedback voltage-divider network may be required to achieve the desired reference voltages. using the feedback voltage-divider allows the maximum output voltage of the converter to be higher than the 1.5v maximum setpoint reference voltage that can be programmed on the sref pin. likewise, the feedback voltage-divider allows the minimum output voltage of the converter to be higher than the fixed 500mv setpoint reference voltage of v set1 . scale the voltage-divider network such that the voltage v fb equals the voltage v sref when the converter output voltage is at the desired level. the voltage-divider relation is given in equation 1: where: -v fb = v sref -r fb is the loop-compensation feedback resistor that connects from the fb pin to the converter output -r ofs is the voltage-scaling programming resistor that connects from the fb pin to the gnd pin the attenuation of the feedback voltage divider is written as: where: - k is the attenuation factor -v sref( lim ) is the v sref voltage setpoint of either 500mv or 1.50v -v out( lim ) is the output voltage of the converter when v sref = v sref( lim ) since the voltage-divider network is in the feedback path, all output voltage setpoints will be attenuated by k , so it follows that all of the setpoint reference voltages will be attenuated by k . it will be necessary then to include the attenuation factor k in all the calculations for selecting the r set programming resistors. the value of offset resistor r ofs can be calculated only after the value of loop-compensation resistor r fb has been determined. the calculation of r ofs is written as equation 3: the setpoint reference voltages are programmed with resistors that use the naming convention r set(x) where (x) is the first, second, third, or fourth programming resistor connected in series starting at the sref pin and ending at the gnd pin. when one of the internal switches closes, it connects the inverting input of the v set amplifier to a specific node among the string of r set programming resistors. all the resistors between that node and the sref pin serve as the feedback impedance r f of the v set amplifier. likewise, all the resistors between that node and the gnd pin serve as the input impedance r in of the v set amplifier. equation 4 gives the general form of the gain equation for the v set amplifier: where: -v ref is the 500mv internal reference of the ic -v set(x) is the resulting setpoint reference voltage that appears at the sref pin component selection for setpoint voltage programming resistors first, determine the attenuation factor k . next, assign an initial value to r set2 of approximately 150k then calculate r set1 using equation 5. the equation for the value of r set1 is written as equation 5: the sum of r set1 and r set2 programming resistors should be approximately 300k , as shown in equation 6, otherwise adjust the value of r set2 and repeat the calculations. equations 7 and 8 give the specific v set gain equations for the ISL62873 setpoint reference voltages. the ISL62873 v set1 setpoint is written as equation 7: the ISL62873 v set2 setpoint is written as equation 8: v fb v out r ofs r fb r ofs + --------------------------------- - ? = (eq. 1) k v sref lim () v out lim () ------------------------------- r ofs r fb r ofs + --------------------------------- - == (eq. 2) table 1. ISL62873 vid truth table state result vid0 close v sref v out 1sw0v set1 v out1 0sw1v set2 v out2 r ofs v set x () r ? fb v out v set x () ? -------------------------------------------- = (eq. 3) v set x ) ( v ref 1 r f r in --------- - + ?? ?? ?? ? = (eq. 4) r set1 r set2 k v set2 v ref ---------------------- - 1 ? ?? ?? ?? ? = (eq. 5) r set1 r set2 + 300k ? (eq. 6) v set1 v ref = (eq. 7) v set2 v ref 1 r set1 r set2 ------------------ + ?? ?? ?? ? = (eq. 8) ISL62873
9 fn6930.0 june 30, 2009 external setpoint reference the ic can use an external setpoint reference voltage as an alternative to vid-selected, re sistor-programmed setpoints. this is accomplished by removing all setpoint programming resistors, connecting the set0 pin to the vcc pin, and feeding the external setpoint reference voltage to the vid0 pin. when set0 and vcc are tied together, the following internal reconfigurations take place: - vid0 pin opens its 500na pull-down current sink - reference source selector switch sw4 moves from int position (internal 500mv) to ext position (vid0 pin) - vid1 pin is disabled the converter will now be in regulation when the voltage on the fb pin equals the voltage on the vid0 pin. as with resistor-programmed setpoints, the reference voltage range on the vid0 pin is 500mv to 1.5v. use equations 1, 2, and 3 beginning on page 8 should it become necessary to implement an output voltage-divider network to make the external setpoint reference voltage compatible with the 500mv to 1.5v constraint. soft-start and voltage-step delay circuit description when the voltage on the vcc pin has ramped above the rising power-on reset voltage v vcc_thr , and the voltage on the en pin has increased above the rising enable threshold voltage v enthr , the sref pin releases its discharge clamp and enables the reference amplifier v set . the soft-start current i ss is limited to 20a and is sourced out of the sref pin into the parallel rc network of capacitor c soft and resistance r t . the resistance r t is the sum of all the series connected r set programming resistors and is written as equation 9: the voltage on the sref pin rises as i ss charges c soft to the voltage reference setpoint selected by the state of the vid inputs at the time the en pin is asserted. the regulator controls the pwm such that t he voltage on the fb pin tracks the rising voltage on the sref pin. once c soft charges to the selected setpoint voltage, the i ss current source comes out of the 20a current limit and decays to the static value set by v sref r t . the elapsed time from when the en pin is asserted to when v sref has reached the voltage reference setpoint is the soft-start delay t ss which is given by equation 10: where: -i ss is the soft-start current source at the 20a limit -v start-up is the setpoint reference voltage selected by the state of the vid inputs at the time en is asserted -r t is the sum of the r set programming resistors the end of soft-start is detected by i ss tapering off when capacitor c soft charges to the designated v set voltage reference setpoint. the ssok flag is set, the pgood pin goes high, and the i ss current source changes over to the voltage-step current source i vs which has a current limit of 100a. whenever the vid inputs or the external setpoint reference, programs a different setpoint reference voltage, the i vs current source charges or discharges capacitor c soft to that new level at 100a. once c soft charges to the selected setpoint voltage, the i vs current source comes out of the 100a current limit and decays to the static value set by v sref r t . the elapsed time to charge c soft to the new voltage is called the voltage-step delay t vs and is given by equation 11: where: -i vs is the 100a setpoint voltage-step current -v new is the new setpoint voltage selected by the vid inputs -v old is the setpoint voltage that v new is changing from -r t is the sum of the r set programming resistors component selection for c soft capacitor choosing the c soft capacitor to meet the requirements of a particular soft-start delay t ss is calculated with equation 12, which is written as: figure 5. ISL62873 voltage programming circuit set0 sref v set + ? sw0 v ref sw1 c soft r set1 r set2 ea + ? fb r ofs r fb v out v comp r t r set1 r set2 r set n () ++ = (eq. 9) t ss r t c soft ? () ? ln 1 v start-up i ss r t ? ----------------------------- - ? () ? = (eq. 10) t vs r t c soft ? () ln 1 v new v old ? () i vs r t ? ------------------------------------------- ? () ? = (eq. 11) c soft t ss ? r t ln 1 v start-up i ss r t ? ----------------------------- - ? () ? ?? ?? ?? --------------------------------------------------------------------- = (eq. 12) ISL62873
10 fn6930.0 june 30, 2009 where: -t ss is the soft-start delay -i ss is the soft-start current source at the 20a limit -v start-up is the setpoint reference voltage selected by the state of the vid inputs at the time en is asserted -r t is the sum of the r set programming resistors choosing the c soft capacitor to meet the requirements of a particular voltage-step delay t vs is calculated with equation 13, which is written as: where: -t vs is the voltage-step delay -v new is the new setpoint voltage -v old is the setpoint voltage that v new is changing from -i vs is the 100a setpoint voltage-step current; positive when v new > v old , negative when v new < v old -r t is the sum of the r set programming resistors fault protection overcurrent the overcurrent protection (o cp) setpoint is programmed with resistor r ocset which is connected across the ocset and phase pins. resistor r o is connected between the vo pin and the actual output voltage of the converter. during normal operation, the vo pin is a high impedance path, therefore there is no voltage drop across r o . the value of resistor r o should always match the value of resistor r ocset . figure 6 shows the overcurrent set circuit. the inductor consists of inductance l and the dc resistance dcr. the inductor dc current i l creates a voltage drop across dcr, which is given by equation 14: the i ocset current source sinks 1 0a into the ocset pin, creating a dc voltage drop across the resistor r ocset , which is given by equation 15: the dc voltage difference between the ocset pin and the vo pin, which is given by equation 16: the ic monitors the voltage of the ocset pin and the vo pin. when the voltage of the ocset pin is higher than the voltage of the vo pin for more than 10s, an ocp fault latches the converter off. component selection for r ocset and c sen the value of r ocset is calculated with equation 17, which is written as: where: -r ocset ( ) is the resistor used to program the overcurrent setpoint -i oc is the output dc load curr ent that will activate the ocp fault detection circuit - dcr is the inductor dc resistance for example, if i oc is 20a and dcr is 4.5m , the choice of r ocset is = 20a x 4.5m /10a = 9k . resistor r ocset and capacitor c sen form an r-c network to sense the inductor current. to sense the inductor current correctly not only in dc operation, but also during dynamic operation, the r-c network time constant r ocset c sen needs to match the inductor time constant l/dcr. the value of c sen is then written as equation 18: for example, if l is 1.5h, dcr is 4.5m , and r ocset is 9k , the choice of c sen = 1.5h/(9k x 4.5m ) = 0.037f . when an ocp fault is declared, the pgood pin will pull-down to 35 and latch off the converter. the fault will remain latched until the en pin has been pulled below the falling en threshold voltage v enthf or if vcc has decayed below the falling por threshold voltage v vcc_thf . undervoltage the uvp fault detection circuit triggers after the fb pin voltage is below the undervoltage threshold v uvth for more than 2s. for example, if the converter is programmed to regulate 1.0v at the fb pin, t hat voltage would have to fall below the typical v uvth threshold of 84% for more than 2s in order to trip the uvp fault latch. in numerical terms, that would be 84% x 1.0v = 0.84v. when a uvp fault is declared, the pgood pin will pull-down to 95 and latch-off the c soft t vs ? r t ln 1 v new v old ? i vs r t ? -------------------------------------- - ? () ? ?? ?? ?? ------------------------------------------------------------------------------ = (eq. 13) figure 6. overcurrent programming circuit phase c o l v o r ocset c sen ocset vo r o dcr i l 10a + _ v dcr + _ v rocset v dcr i l dcr ? = (eq. 14) v rocset 10 ar ocset ? = (eq. 15) v ocset v ? vo v dcr v ? rocset i l dcr ? i ocset r ocset ? ? == (eq. 16) (eq. 17) r ocset i oc dcr ? i ocset ---------------------------- = (eq. 18) c sen l r ocset dcr ? ------------------------------------------ = ISL62873
11 fn6930.0 june 30, 2009 converter. the fault will remain latched until the en pin has been pulled below the falling en threshold voltage v enthf or if vcc has decayed below the falling por threshold voltage v vcc_thf . over-temperature when the temperature of the ic increases above the rising threshold temperature t otrth , it will enter the otp state that suspends the pwm, forcing the lgate and ugate gate-driver outputs low. the st atus of the pgood pin does not change nor does the converter latch-off. the pwm remains suspended until the ic temperature falls below the hysteresis temperature t othys at which time normal pwm operation resumes. the otp state can be reset if the en pin is pulled below the falling en threshold voltage v enthf or if vcc has decayed below the falling por threshold voltage v vcc_thf . all other protection circuits remain functional while the ic is in the otp state. it is likely that the ic will detect an uvp fault because in the absence of pwm, the output voltage decays below the undervoltage threshold v uvth . theory of operation the modulator features intersil?s r 3 robust-ripple- regulator technology, a hybrid of fixed frequency pwm control and variable frequency hysteretic control. the pwm frequency is maintained at 300khz under static continuous-conduction-mode operation within the entire specified envelope of input volt age, output voltage, and output load. if the application sh ould experience a rising load transient and/or a falling line transient such that the output voltage starts to fall, the modulator will extend the on-time and/or reduce the off-time of the pwm pulse in progress. conversely, if the application should experience a falling load transient and/or a rising line transient such that the output voltage starts to rise, the modulator will truncate the on-time and/or extend the off-time of the pwm pulse in progress. the period and duty cycle of the ensuing pwm pulses are optimized by the r 3 modulator for the remainder of the transient and work in concert with the error amplifier v err to maintain output voltage regulation. once the transient has dissipated and the control loop has recovered, the pwm frequency returns to the nominal static 300khz. modulator the r 3 modulator synthesizes an ac signal v r , which is an analog representation of the output inductor ripple current. the duty-cycle of v r is the result of charge and discharge current through a ripple capacitor c r . the current through c r is provided by a transconductance amplifier g m that measures the input voltage (v in ) at the phase pin and output voltage (v out ) at the vo pin. the positive slope of v r can be written as equation 19: the negative slope of v r can be written as equation 20 : where, g m is the gain of the transconductance amplifier. a window voltage v w is referenced with respect to the error amplifier output voltage v comp , creating an envelope into which the ripple voltage v r is compared. the amplitude of v w is controlled internally by the ic. the v r, v comp, and v w signals feed into a window comparator in which v comp is the lower threshold voltage and v w is the higher threshold voltage. figure 7 shows pwm pulses being generated as v r traverses the v w and v comp thresholds. the pwm switching frequency is proporti onal to the slew rates of the positive and negative slopes of v r; it is inversely proportional to the voltage between v w and v comp. synchronous rectification a standard dc/dc buck regulator uses a free-wheeling diode to maintain uninterrupted current conduction through the output inductor when the high-side mosfet switches off for the balance of the pwm switching cycle. low conversion efficiency as a result of the conduction loss of the diode makes this an unattractive option for all but the lowest current applications. efficien cy is dramatically improved when the free-wheeling diode is replaced with a mosfet that is turned on whenever the high-side mosfet is turned off. this modification to t he standard dc/dc buck regulator is referred to as synchronous rectification, the topology implemented by the ISL62873 controller. diode emulation the polarity of the output indu ctor current is defined as positive when conducting away from the phase node, and defined as negative when conducting towards the phase node. the dc component of the inductor current is positive, but the ac component known as the ripple current, can be either positive or negative. should the sum of the ac and dc components of the inductor current remain positive for the entire switching period, the converter is in v rpos g m () v in v out ? () c r ? ? = (eq. 19) v rneg g m v out c r ? ? = (eq. 20) figure 7. modulator waveforms during load transient pwm ripple capacitor voltage c r window voltage v w error amplifier voltage v comp ISL62873
12 fn6930.0 june 30, 2009 continuous-conduction-mode (ccm.) however, if the inductor current becomes negati ve or zero, the converter is in discontinuous-conduction-mode (dcm.) unlike the standard dc/dc buck regulator, the synchronous rectifier can sink current from the output filter inductor during dcm, reducing the light-load efficiency with unnecessary conduction loss as the low-side mosfet sinks the inductor current. the ISL62873 controller avoids the dcm conduction loss by making the low-side mosfet emulate the current- blocking behavior of a diode. this smart-diode operation called diode-emulation-mode (dem) is triggered when the negative inductor current prod uces a positive voltage drop across the r ds(on) of the low-side mosfet for eight consecutive pwm cycles while the lgate pin is high. the converter will exit dem on the next pwm pulse after detecting a negative voltage across the r ds(on) of the low- side mosfet. it is characteristic of the r 3 architecture for the pwm switching frequency to decrease while in dcm, increasing efficiency by reducing unnecessary gate-driver switching losses. the extent of the frequency reduction is proportional to the reduction of load current. upon entering dem, the pwm frequency is forced to fall approximately 30% by forcing a similar increase of the window voltage v w . this measure is taken to prevent oscillating between modes at the boundary between ccm and dcm. the 30% increase of v w is removed upon exit of de m, forcing the pwm switching frequency to jump back to the nominal ccm value. power-on reset the ic is disabled until the voltage at the vcc pin has increased above the rising power-on reset (por) threshold voltage v vcc_thr . the controller will become disabled when the voltage at the vcc pin decreases below the falling por threshold voltage v vcc_thf . the por detector has a noise filter of approximately 1s. v in and pvcc voltage sequence prior to pulling en above the v enthr rising threshold voltage, the following criteria must be met: -v pvcc is at least equivalent to the vcc rising power-on reset voltage v vcc_thr -v vin must be 3.3v or the minimum required by the application start-up timing once vcc has ramped above v vcc_thr , the controller can be enabled by pulling the en pin voltage above the input-high threshold v enthr . approximately 20s later, the voltage at the sref pin begins slewing to the designated vid set-point. the converter output voltage at the fb feedback pin follows the voltage at the sref pin. during soft-start, the regulator always operates in ccm until the soft-start sequence is complete. pgood monitor the pgood pin indicates when the converter is capable of supplying regulated voltage. the pgood pin is an undefined impedance if the vcc pin has not reached the rising por threshold v vcc_thr , or if the vcc pin is below the falling por threshold v vcc_thf . the pgood pull-down resistance corresponds to a specific protective fault, thereby reducing troubleshooting time and effort. table 2 maps the pull-down resistance of the pgood pin to the corresponding fault status of the controller. lgate and ugate mosfet gate-drivers the lgate pin and ugate pins are mosfet driver outputs. the lgate pin drives the low-side mosfet of the converter while the ugate pin drives the high-side mosfet of the converter. the lgate driver is optimized for low duty-cycle applications where the low-side mosfet experiences long conduction times. in this environment, the low-side mosfets require exceptionally low r ds(on) and tend to have large parasitic charges that conduct transient currents within the devices in respon se to high dv/dt switching present at the phase node. the drain-gate charge in particular can conduct sufficient current through the driver pull-down resistance that the v gs(th) of the device can be exceeded and turned on. for this reason the lgate driver has been designed with low pull-down resistance and high sink current capability to ensure clamping the mosfets gate voltage below v gs(th) . table 2. pgood pull-down resistance condition pgood resistance vcc below por undefined soft-start or undervoltage 95 overcurrent 35 figure 8. gate driver adaptive shoot-through 1v 1v ugate lgate 1v 1v ISL62873
13 fn6930.0 june 30, 2009 adaptive shoot-through protection adaptive shoot-through protection prevents a gate-driver output from turning on until t he opposite gate-driver output has fallen below approximately 1v. the dead-time shown in figure 8 is extended by the additional period that the falling gate voltage remains above the 1v threshold. the high-side gate-driver output voltage is measured across the ugate and phase pins while the lo w-side gate-driver output voltage is measured across the lgate and pgnd pins. the power for the lgate gate-driver is sourced directly from the pvcc pin. the power for the ugate gate-driver is supplied by a boot-strap capacitor connected across the boot and phase pins. the capacitor is charged each time the phase node voltage falls a diode drop below pvcc such as when the low-side mosfet is turned on. compensation design figure 9 shows the recommended type-ii compensation circuit. the fb pin is the inverting input of the error amplifier. the comp signal, the output of t he error amplifier, is inside the chip and unavailable to users. c int is a 100pf capacitor integrated inside the ic, connecting across the fb pin and the comp signal. r fb , r comp , c comp and c int form the type-ii compensator. the frequency domain transfer function is given by equation 21: the lc output filter has a double pole at its resonant frequency that causes rapid phase change. the r 3 modulator used in the ic makes the lc output filter resemble a first order system in which the closed loop stability can be achieved with the recommended type-ii compensation network. intersil provides a pc-based tool that can be used to calculate compensation network component values and help simulate the loop frequency response. general application design guide this design guide is intended to provide a high-level explanation of the steps neces sary to design a single-phase power converter. it is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. in addition to this guide, intersil provides complete reference designs that include sc hematics, bills of materials, and example board layouts. selecting the lc output filter the duty cycle of an ideal buck c onverter is a function of the input and the output voltage. this relationship is expressed in equation 22: the output inductor peak-to-peak ripple current is expressed in equation 23: a typical step-down dc/dc converter will have an i p-p of 20% to 40% of the maximum dc output load current. the value of i p-p is selected based upon several criteria such as mosfet switching loss, inducto r core loss, and the resistive loss of the inductor winding. the dc copper loss of the inductor can be estimated using equation 24: where, i load is the converter output dc current. the copper loss can be significant so attention has to be given to the dcr selection. another fa ctor to consider when choosing the inductor is its saturation characteristics at elevated temperature. a saturated induct or could cause destruction of circuit components, as well as nuisance ocp faults. a dc/dc buck regulator must have output capacitance c o into which ripple current i p-p can flow. current i p-p develops a corresponding ripple voltage v p-p across c o, which is the sum of the voltage drop across the capacitor esr and of the voltage change stemming from charge moved in and out of the capacitor. these two voltages are expressed in equations 25 and 26: if the output of the converter has to support a load with high pulsating current, several capacitors will need to be paralleled to reduce the total esr until the required v p-p is achieved. the inductance of the capacitor can cause a brief voltage dip if the load transient has an extremely high slew rate. low inductance capacitors should be considered. a capacitor dissipates heat as a function of rms current and frequency. be sure that i p-p is shared by a sufficient quantity of paralleled capacitors so that they operate below the maximum rated rms current at f sw . take into account that the rat ed value of a capacitor can fade as much as 50% as the dc voltage across it increases. selection of the input capacitor the important parameters for the bulk input capacitance are the voltage rating and the rms current rating. for reliable operation, select bulk capacitors with voltage and current (eq. 21) g comp s () 1sr fb r comp + () c ? comp ? + sr fb c int 1sr comp c ? comp ? + () ?? ? --------------------------------------------------------------------------------------------------------------- = r ofs ea + fb c int = 100pf - sref v out figure 9. compensation reference circuit r fb r comp c comp comp d v o v in --------- = (eq. 22) (eq. 23) i p-p v o 1d ? () ? f sw l ? ------------------------------ - = (eq. 24) p copper i load 2 dcr ? = v esr i p-p e ? sr = (eq. 25) ? v c i p-p 8c o f ? sw ? --------------------------------- = (eq. 26) ISL62873
14 fn6930.0 june 30, 2009 ratings above the maximum input voltage and capable of supplying the rms current requir ed by the switching circuit. their voltage rating should be at least 1.25x greater than the maximum input voltage, while a voltage rating of 1.5x is a preferred rating. figure 10 is a graph of the input rms ripple current, normalized relative to output load current, as a function of duty cycle that is adjusted for converter efficiency. the ripple current calculation is written as equation 27: where: -i max is the maximum continuous i load of the converter - x is a multiplier (0 to 1) corresponding to the inductor peak-to-peak ripple amplitude expressed as a percentage of i max (0% to 100%) - d is the duty cycle that is adjusted to take into account the efficiency of the converter duty cycle is written as equation 28: in addition to the bulk capacitance, some low esl ceramic capacitance is recommended to decouple between the drain of the high-side mosfet and the source of the low-side mosfet. selecting the bootstrap capacitor adding an external capacitor across the boot and phase pins completes the bootstrap circuit. we selected the bootstrap capacitor breakdown voltage to be at least 10v. although the theoretical maximum voltage of the capacitor is pvcc-v diode (voltage drop across the boot diode), large excursions below ground by the phase node requires we select a capacitor with at least a breakdown rating of 10v. the bootstrap capacitor can be chosen from equation 29: where: -q gate is the amount of gate charge required to fully charge the gate of the upper mosfet - v boot is the maximum decay across the boot capacitor as an example, suppose an upper mosfet has a gate charge, q gate , of 25nc at 5v and also assume the droop in the drive voltage over a pwm cycl e is 200mv. one will find that a bootstrap capacitance of at le ast 0.125f is required. the next larger standard value capacitance is 0.15f. a good quality ceramic capacitor such as x7r or x5r is recommended. driver power dissipation switching power dissipation in the driver is mainly a function of the switching frequency and total gate charge of the selected mosfets. calculating the power dissipation in the driver for a desired application is critical to ensuring safe operation. exceeding the maximum allowable power dissipation level will push the ic beyond the maximum recommended operating juncti on temperature of +125c. when designing the application, it is recommended that the following calculation be performed to ensure safe operation at the desired frequency for the selected mosfets. the power dissipated by the drivers is approximated as equation 30: where: -f sw is the switching frequency of the pwm signal -v u is the upper gate driver bias supply voltage -v l is the lower gate driver bias supply voltage -q u is the charge to be delivered by the upper driver into the gate of the mosfet and discrete capacitors -q l is the charge to be delivered by the lower driver into the gate of the mosfet and discrete capacitors -p l is the quiescent power consumption of the lower driver -p u is the quiescent power consumption of the upper driver (eq. 27) i in_rms i max 2 dd 2 ? () ? () xi max 2 d 12 ------ ?? ?? ?? + i max ---------------------------------------------------------------------------------------------------- - = (eq. 28) d v o v in eff ? -------------------------- = figure 10. normalized rms input current for x = 0.8 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 normalized input rms ripple current duty cycle x = 1 x = 0.75 x = 0.50 x = 0.25 x = 0 c boot q gate v boot ----------------------- - (eq. 29) figure 11. boot capacitance vs boot ripple voltage 20nc v boot_cap (v) c boot_cap (f) 2.0 1.6 1.4 1.0 0.8 0.6 0.4 0.2 0.0 0.3 0.0 0.1 0.2 0.4 0.5 0.6 0.9 0.7 0.8 1.0 q gate = 100nc 1.2 1.8 50n c pf sw 1.5v u q u v l q l + () p l p u ++ = (eq. 30) ISL62873
15 fn6930.0 june 30, 2009 mosfet selection and considerations typically, a mosfet cannot tolerate even brief excursions beyond their maximum drain to source voltage rating. the mosfets used in the power stage of the converter should have a maximum v ds rating that exceeds the sum of the upper voltage tolerance of the input power source and the voltage spike that occurs wh en the mosfet switches off. there are several power mosfets readily available that are optimized for dc/dc converter applications. the preferred high-side mosfet emphasizes low switch charge so that the device spends the least amount of time dissipating power in the linear region. unlike the low-side mosfet which has the drain-source voltage clamped by its body diode during turn-off, the high-side mosfet turns off with v in -v out , plus the spike, across it. the preferred low-side mosfet emphasizes low r ds(on) when fully saturated to minimize conduction loss. for the low-side mosfet, (ls), the power loss can be assumed to be conductive only and is written as equation 31: for the high-side mosfet, (hs), its conduction loss is written as equation 32: for the high-side mosfet, its sw itching loss is written as equation 33: where: -i valley is the difference of the dc component of the inductor current minus 1/2 of the inductor ripple current -i peak is the sum of the dc component of the inductor current plus 1/2 of the inductor ripple current -t on is the time required to drive the device into saturation -t off is the time required to drive the device into cut-off layout considerations the ic, analog signals, and logic signals should all be on the same side of the pcb, located away from powerful emission sources. the power conversion components should be arranged in a manner similar to the example in figure 13 where the area enclosed by the current circulating through the input capacitors, high-side mosfets, and low-side mosfets is as small as possible and all located on the same side of the pcb. the power components can be located on either side of t he pcb relative to the ic. signal ground the gnd pin is the signal-common also known as analog ground of the ic. when laying out the pcb, it is very important that the connection of the gnd pin to the bottom setpoint-reference programm ing-resistor, bottom feedback voltage-divider resistor (if used), and the csoft capacitor be made as close as possible to the gnd pin on a conductor not shared by any other components. in addition to the critical single point connection discussed in the previous paragraph, the ground plane layer of the pcb should have a single-point-connected island located under the area encompassing the ic, setpoint reference programming components, feedback voltage divider components, compensation components, csoft capacitor, and the interconnecting traces among the components and the ic. the island should be connected using se veral filled vias to the rest of the ground plane layer at one poi nt that is not in the path of either large static currents or high di/dt currents. the single connection point should also be where the vcc decoupling capacitor and the gnd pin of the ic are connected. power ground anywhere not within the analog-ground island is power ground. vcc and pvcc pins place the decoupling capacitors as close as practical to the ic. in particular, the pvcc decoupling capacitor should have a very short and wide connection to the pgnd pin. the vcc decoupling capacitor should not share any vias with the pvcc decoupling capacitor. figure 12. power dissipation vs frequency frequency (hz) 0 100 200 300 400 500 600 700 800 900 1000 0 200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k power (mw) q u = 50nc q l = 50nc q u = 50nc q l = 100nc q u = 20nc q l = 50nc q u = 100nc q l = 200nc (eq. 31) p con_ls i load 2 r ? ds on () _ls 1d ? () ? (eq. 32) p con_hs i load 2 r ? ds on () _hs d ? = (eq. 33) p sw_hs v in i valley t on f ? sw ?? 2 --------------------------------------------------------------------- - v in i peak t off f ? sw ?? 2 ----------------------------------------------------------------- - + = figure 13. typical power component placement vin vout phase node gnd output capacitors low-side mosfets input capacitors + + high-side mosfets ISL62873
16 fn6930.0 june 30, 2009 en, pgood, vid0, and vid1 pins these are logic signals that are referenced to the gnd pin. treat as a typical logic signal. ocset and vo pins the current-sensing network consisting of r ocset , r o , and c sen needs to be connected to the inductor pads for accurate measurement of the dcr voltage drop. these components however, should be located physically close to the ocset and vo pins with traces leading back to the inductor. it is critical that the traces are shielded by the ground plane layer all the way to the inductor pads. the procedure is the same fo r resistive current sense. fb, sref, set0, set1, and set2 pins the input impedance of these pins is high, making it critical to place the loop compensation components, setpoint reference programming resistors, feedback voltage divider resistors, and csoft close to the ic, keeping the length of the traces short. lgate, pgnd, ugate, boot, and phase pins the signals going through these traces are high dv/dt and high di/dt, with high peak charging and discharging current. the pgnd pin can only flow current from the gate-source charge of the low-side mosfets when lgate goes low. ideally, route the trace from the lgate pin in parallel with the trace from the pgnd pin, route the trace from the ugate pin in parallel with th e trace from the phase pin, and route the trace from the bo ot pin in parallel with the trace from the phase pin. these pairs of traces should be short, wide, and away from other traces with high input impedance; weak signal traces should not be in proximity with these traces on any layer. copper size for the phase node the parasitic capacitance and parasitic inductance of the phase node should be kept very low to minimize ringing. it is best to limit the size of the phase node copper in strict accordance with the current and thermal management of the application. an mlcc should be connected directly across the drain of the upper mosfet and the source of the lower mosfet to suppress the turn-off voltage spike. ISL62873
17 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6930.0 june 30, 2009 ISL62873 ultra thin quad flat no-lead plastic package (utqfn) 6 b e a d 0.10 c 2x c 0.05 c a 0.10 c a1 seating plane index area 2 1 n top view bottom view side view nx (b) section "c-c" e cc 5 c l terminal tip (a1) l 0.10 c 2x e l1 nx l 2 1 0.10 m c a b 0.05 m c 5 nx b (datum b) (datum a) pin #1 id 16x 3.00 1.40 2.20 0.40 0.50 0.20 0.40 0.20 0.90 1.40 1.80 land pattern 10 k l16.2.6x1.8a 16 lead ultra thin quad flat no-lead plastic package symbol millimeters notes min nominal max a 0.45 0.50 0.55 - a1 - - 0.05 - a3 0.127 ref - b 0.15 0.20 0.25 5 d 2.55 2.60 2.65 - e 1.75 1.80 1.85 - e 0.40 bsc - k0.15 - - - l 0.35 0.40 0.45 - l1 0.45 0.50 0.55 - n162 nd 4 3 ne 4 3 0- 12 4 rev. 5 2/09 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on d and e side, respectively. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. maximum package warpage is 0.05mm. 8. maximum allowable burrs is 0.076mm in all directions. 9. jedec reference mo-255. 10. for additional information, to assist with the pcb land pattern design effort, see intersil technical brief tb389.

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